The present invention relates to a PLL (Phase-Locked Loop) circuit and, more particularly, to a PLL circuit capable of obtaining an oscillation frequency with a small step interval.
In general, a PLL circuit has an arrangement like the one shown in FIG. 9. This PLL circuit includes a VCO (Voltage-Controlled Oscillator) 41 capable of controlling the oscillation frequency in accordance with a control voltage, a frequency divider 42 for frequency-dividing the oscillation frequency of the VCO 41 by a frequency division ratio determined by an external set value, a phase comparator 43 for comparing the phases of the frequency division output and a reference frequency signal with each other to generate phase difference information so as to obtain a control voltage for the VCO 41. Assume that the phase comparator 43 has a filter function for generating a pulse-like signal component every time phase comparison is performed, and extracting a DC component and a low-frequency component near the DC component from the pulse-like signal.
In this PLL circuit, letting 1/k be the frequency division of the frequency divider 42, and fref be the frequency of the reference frequency signal, an output oscillation frequency fosc is given by EQU fosc=k.times.fref
In this case, in consideration of a frequency division value k as an integer, an oscillation frequency with a frequency step interval fref can be obtained by this PLL circuit.
In order to obtain an oscillation frequency with a smaller frequency step interval by using this PLL circuit, the reference frequency fref may be decreased. If, however, the reference frequency fref is decreased, the cutoff frequency of the filter of the phase comparator 43 must also be set low. With a decrease in the cutoff frequency of the filter of the phase comparator 43, the time constant of the filter increases. As a result, it takes time to stabilize the output from the filter. That is, as the frequency step interval of the oscillation frequency obtained by this PLL circuit decreases, the time required for the stabilization of the output oscillation frequency prolongs with respect t6 switching of oscillation frequencies.
FIG. 10 shows a PLL circuit which can solve such a problem. This PLL circuit includes a VCO 51, a first frequency divider 52 for frequency-dividing a frequency signal from the VCO 51, a second frequency divider 53 for further frequency-dividing the signal frequency-divided by the first frequency divider 52, a phase comparator 54 for comparing the phases of the signal frequency-divided by the first frequency divider 52 and a reference frequency signal with each other, a triangular wave generator 55 for generating a triangular wave on the basis of the signal frequency-divided by the second frequency divider 53, and an adder 56 for adding the output signal from the phase comparator 54 to the output signal from the triangular wave generator 55. Note that the adder 56 has a filter for sufficiently blocking a pulse-like signal component generated every time phase comparison is performed.
In this PLL circuit, a signal input to the first frequency divider 52 is frequency-divided by k or (k+j) (j is an integer other than 0) on the basis of a signal frequency-divided by the second frequency divider 53. The frequency-divided signal is input to the phase comparator 54, in which the phase of the signal is compared with that of the reference frequency signal. The signal frequency-divided by the first frequency divider 52 is input to the second frequency divider 53 to be further frequency-divided by s. The signal frequency-divided by the second frequency divider 53 is input to the triangular wave generator 55. In addition, the second frequency divider 53 outputs a switching signal to the first frequency divider 52 at a predetermined timing to switch k-frequency division and (k+j)-frequency division.
The triangular wave generator 55 generates a triangular wave with a period s on the basis of the frequency division signal from the second frequency divider 53. The comparison result from the phase comparator 54 and the triangular wave from the triangular wave generator 55 are added (or subtracted from each other) by the adder 56. With this operation, a fluctuation signal with the period s is removed from the comparison result from the phase comparator 54. An output signal from the phase comparator 54 is then supplied, as a frequency control signal, to the VCO 51.
Assume that in this PLL circuit, the first frequency divider 52 performs (k+1)-frequency division m times and k-frequency division (s-m) times during the period s. The oscillation frequency fosc is then given by EQU fosc=fref.times.{k+(m/s)}
As is apparent, an oscillation frequency with a frequency step interval (fref/s) can be obtained. That is, an oscillation frequency with a small frequency step interval can be obtained by using the PLL circuit in FIG. 10 without decreasing the reference frequency fref.
In the method of decreasing the frequency step interval of an oscillation frequency by canceling out a fluctuation component having a long period and included in a phase error signal by using a triangular wave, an error in the triangular wave directly affects the oscillation frequency of the VCO 51, resulting in deterioration in the stability of the oscillation frequency.